Hardware Acceleration for Medical Imaging
Making the best reconstruction algorithm fast enough to actually use.
Iterative algorithms like Maximum Likelihood Expectation Maximization produce the highest-quality tomographic images and take the longest to compute: which is precisely why clinics often cannot use them. This work treats that as an engineering constraint rather than a fact of life, implementing a dedicated acceleration framework across FPGA fabric and DSP vision pipelines.
MLEM speed-up on FPGA over optimised Xeon software
- FPGA acceleration (MLEM)
- 288×
- DSP processing acceleration
- 250%
- Xilinx VC709 platform
- Virtex-7
- Citations, IEEE Access 2019
- 44
Summary
What the work set out to do, and the reasoning that shaped it.
This research addresses the computational bottleneck in tomographic medical imaging. While iterative algorithms like Maximum Likelihood Expectation Maximization (MLEM) provide high-quality images, their long execution times often prevent real-time clinical use.
The response was a dedicated hardware acceleration framework using FPGAs and DSPs: moving the mathematics off general-purpose processors and onto fabric designed to exploit its parallelism.
The FPGA work implemented a parallel structure for MLEM on a Xilinx Virtex-7 VC709 using High-Level Synthesis, achieving a 288× speed-up compared to optimised software execution on an Intel Xeon workstation. Separately, a dual-core Blackfin ADSP-BF609 with an embedded Pipelined Vision Processor delivered a 250% acceleration for clinical post-processing tasks.
Impact
What changed as a result.
A 288× speed-up over optimised Xeon software execution moves MLEM reconstruction from a batch operation into the interactive regime.
The DSP framework accelerated diagnostic calculations: Thyroid Uptake Ratio and Glomerular Filtration Rate among them: by 250%, addressing the post-scan analysis path rather than only reconstruction.
Together, the two frameworks facilitate real-time diagnostic imaging, allowing rapid access to medical images during critical, time-sensitive healthcare procedures.
The IEEE Access paper documenting the FPGA architecture is the most-cited output of the research programme.
Figures
The work, drawn.
Purpose-built diagrams: each one carries an idea that prose alone would take a page to deliver.
The MLEM bottleneck
Forward projection, comparison, back projection, update: repeated until convergence. Quality comes from iteration; so does the delay.
Parallel architecture on Virtex-7
Restructuring MLEM to expose its latent data parallelism, then mapping it onto FPGA fabric via High-Level Synthesis.
288× against optimised software
Measured against optimised software execution on an Intel Xeon workstation: not against a naive baseline.
Pipelined Vision Processor path
The ADSP-BF609's PVP handles clinical post-processing: uptake ratios and filtration rates: at 250% of software speed.
Methods
How it was done.
Parallel MLEM on FPGA fabric
MLEM's iterative structure hides substantial data parallelism inside its forward and back projection steps. Restructuring the algorithm to expose that parallelism is what makes an FPGA implementation worthwhile rather than merely different.
High-Level Synthesis
HLS was used to target the Xilinx Virtex-7 VC709, allowing the parallel architecture to be expressed and iterated at a higher level of abstraction than register-transfer design.
Pipelined Vision Processor
The Analog Devices ADSP-BF609's embedded PVP provides a hardware pipeline for image operations, used here for clinical post-processing rather than reconstruction.
Diagnostic calculation offload
Thyroid Uptake Ratio and Glomerular Filtration Rate calculations were moved onto the accelerated DSP path, producing a 250% improvement in processing speed.
Specifications
The numbers.
Development timeline
From simulation to the clinic.
System-on-Chip formulation
A novel System on Chip design for thyroid imaging studies presented at IEEE ICAECCT: the first formulation of the accelerated pipeline.
Low-cost real-time platform
A practical design and implementation of a low-cost platform for real-time diagnostic imaging published in IEEE Access.
DSP acceleration framework
ADSP-BF609 with Pipelined Vision Processor applied to clinical post-processing, achieving 250% acceleration on diagnostic calculations.
FPGA parallel architecture
Parallel MLEM on Xilinx Virtex-7 VC709 via HLS achieves 288× speed-up. Published in IEEE Access; the programme's most-cited work.
Outcomes
- 288× MLEM reconstruction speed-up on Xilinx Virtex-7 VC709 FPGA
- 250% acceleration of clinical post-processing on ADSP-BF609 with PVP
- Two IEEE Access journal papers (2017, 2019)
- IEEE ICAECCT conference paper on System-on-Chip thyroid imaging (2016)
- Real-time diagnostic imaging made feasible for time-sensitive procedures
Collaborators & support
- Sri Sathya Sai Institute of Higher Learning
- A. Sewa
- S. S. S. Sanagapati
- T. G. Shashidhara
- S. Sivaramakrishnan
Funded under
DST · INR 96 Lakhs
2016-2021 · Project Associate
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